Nonvolatile semiconductor memory devices (also referred to as nonvolatile memories) are utilized as recording media of various products such as digital cameras, portable audio players and cellular phones. Research and development of the nonvolatile semiconductor memory devices have been actively conducted to meet the various needs of the market, for example, further reduction in the size of the product, increase in recording capacity, increase in the response speed of recording and reading, and reduction in power consumption.
As one of the ways to meet the aforementioned needs of the market, in recent years, a nonvolatile memory of a so-called SOI (silicon on insulator) type has been actively developed, in which elements are formed using silicon (Si) that is provided over an insulating film.
The following methods and the like are known for forming an SOI substrate in an SOI nonvolatile memory: a method in which oxygen molecules are implanted from a silicon crystal surface by ion implantation, and then oxidation at a high temperature is performed, whereby an insulating film of silicon oxide is formed in the silicon crystal; and a method in which two silicon wafers are prepared, a portion used for separation by ion implantation is formed in one of the silicon wafers, the two silicon wafers are bonded to each other, and then, one of the silicon wafers is separated.
On the other hand, in order to achieve cost reduction, a structure in which a memory transistor is provided over a glass substrate or a plastic substrate has been proposed (e.g., patent document 1).
In a conventional memory transistor, an island-shaped semiconductor layer 601 formed of silicon, a first insulating film 602 (also referred to as a tunnel insulating film), a floating gate 603 (FG), a second insulating film 604, and a control gate 605 (CG) are stacked over a substrate 600, and the floating gate 603 is electrically insulated (floated). Further, a source line (SL) is electrically connected to one of impurity regions 606 and 607 which function as a source or a drain and are provided in the semiconductor layer 601, and a bit line (BL) is electrically connected to the other of the impurity regions 606 and 607 (see FIG. 11).
Further, in a nonvolatile memory using a floating gate, data is stored in accordance with the amount of charge accumulated in the floating gate 603. The floating gate 603 is electrically insulated; thus, voltage is indirectly applied between the semiconductor layer 601 and the floating gate 603 by using the control gate 605, whereby the memory transistor is operated.
When electrons are accumulated in the floating gate 603, voltage that has been applied to the control gate 605 is less likely to be applied between the semiconductor layer 601 and the floating gate 603 compared to the state where electrons are not accumulated; accordingly, the threshold value of the memory transistor apparently shifts in the positive direction. That is, by detecting the amount of charge accumulated in the floating gate 603 with change in the threshold value of the memory transistor, data stored in the memory transistor can be read out.
Here, if the impurity regions 606 and 607 of the semiconductor layer 601 have the same potential, the potential of the floating gate 603, VFG, and a change in the threshold value of the memory transistor, ΔVtm, can be represented by the following formula.
                              V          FG                =                                            C              2                                                      C                1                            +                              C                2                                              ⁢                      (                                          V                CG                            -                              Δ                ⁢                                                                  ⁢                Vtm                                      )                                              [                  Formula          ⁢                                          ⁢                      (            1            )                          ]                                          Δ          ⁢                                          ⁢          Vtm                =                  -                                    Q              FG                                      C              2                                                          [                  Formula          ⁢                                          ⁢                      (            2            )                          ]            
In the formulas (1) and (2), VCG is the potential of the control gate 605; C1, the capacitance between the semiconductor layer 601 and the floating gate 603; C2, the capacitance between the floating gate 603 and the control gate 605; and QFG, the amount of electric charges in the floating gate 603. Note that C2/(C1+C2) in the formula (1) is generally referred to as a coupling ratio. As the coupling ratio increases, the ratio of the voltage applied between the semiconductor layer 601 and the floating gate 603 to the voltage applied to the control gate 605 increases.
When data is to be written to the memory transistor, high voltage of a positive polarity is applied to the control gate 605 by an F-N (Fowler-Nordheim) tunneling current or hot electrons so that a voltage is indirectly applied between the semiconductor layer 601 and the floating gate 603, whereby electrons are injected into the floating gate 603. On the other hand, when data is to be erased from the memory, a high voltage of a negative polarity is applied to the control gate 605 by an F-N (Fowler-Nordheim) tunneling current or the like so that a voltage is indirectly applied between the semiconductor layer 601 and the floating gate 603, whereby electrons are released from the floating gate 603. Thus, the voltage can be efficiently applied between the semiconductor layer 601 and the floating gate 603 by increasing the coupling ratio, so that a writing voltage and an erasing voltage can be reduced.